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Freescale Semiconductor Technical Data
Document order number: MPC18730
Rev 1.0, 10/2005
Power Management IC with Five Regulated Outputs Programmed Through 3-Wire Serial Interface
The MPC18730 Power Management IC (PMIC) regulates five independent output voltages from either a single cell Li-Ion (2.7 V to 4.2 V input range) or from a single cell Ni-MH or dry cell (0.9 V to 2.2 V input range). The PMIC includes 2 DC-DC converters and 3 low drop out (LDO) linear regulators. The output voltage for each of the 5 output voltages is set independently through a 3-wire serial interface. The serial interface also configures the PMIC's versatile start-up control system, which includes multiple wakeup, sleep, standby, and reset modes to minimize power consumption for portable equipment. In single cell Li-Ion applications two DC-DC converters are configured as buck (step-down) regulators. In single cell Ni-MH or dry cell applications, one DC-DC converter is configured as a boost (step-up) regulator, and the other as buck-boost regulator. The DCDC converters' output voltages have set ranges 1.613 V to 3.2 V at up to 120 mA, and 0.805 V to 1.5 V up to 100 mA through the serial interface.
Device
18730
POWER MANAGEMENT IC
EP SUFFIX 98ARL10571D 64-TERMINAL 0.5 mm PITCH QFN
ORDERING INFORMATION
Temperature Range (TA) -10C to 65C Package 64 QFN
Features * Operates from single cell Li-Ion, Ni-MH, or Alkaline * 2 DC-DC Converters * 3 Low Drop Regulators * Serial Interface Sets Output Voltages * 4 Wake Inputs * Low Current Standby Mode * Pb-Free Packaging Designated by Suffix Code EP MPC18730 2.7 V to 4.2 V Input VB
VB VO VREF RSTO1B EXT_G_ON
VO
MPC18730EP/R2
VCC1 VO1 SW1 VCC2 VO2
Programmable 1.613 V to 3.2 V Programmable 0.805 V to 1.5 V
MCU
SW2 SREGI1 SREGO1 RSTO2B SREGI2 CONTROL SREGO2 SREGI3 LOGIC SREGO3 INPUTS GND PGND VG SWG VB
Programmable 0.865 V to 2.8 V Programmable 0.011 V to 2.8 V Programmable 2.08 V to 2.8 V
Figure 1. MPC18730 Simplified Application Diagram
* This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice.
(c) Freescale Semiconductor, Inc., 2005. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
HVB VMODE LVB Driver VREF RSTO1B(Int) VREF CLR LSWO VO1 RSTO1B RESET Block 1 CRST1 RST1ADJ INM1 RF1 VG DTC1 VO1 RSTO2B RESET Block 2 RSTO2B(Int) VG RSTO2B(Int) POWER SWITCH2 VCC2 VO2IN VO2 DW_2T REF2 Step-UpDown DC/DC Converter CH2 DW_2B VI2 SW2 Step-UpDown DC/DC Converter CH1 VMODE VO1 RSTO1B(Int) BANDGAP REFERENCE VG VB VB LVB VO1 V_STBY VCC1 VO1 VI1
RSTO2B(Int) POWER RSTO1B(Int) VO1 VG SWITCH1
SW1 PGND1
CRST2 INM2 RF2
DTC2 VG REF3 SREGC1 Series Pass Regulator1 VG SREGC2 SREGC3 WAKE1B WAKE2B WAKE3B WAKE4B SEQSEL DATA STRB SCKIN CLR SLEEP CLKIN GND VGSEL1 VGSEL2 WDT REF4 V_STBY VO1 VB REF5 RSTO1B(Int) RSTO2B CONTROL (Int) SEQSEL Control Logic Series Pass Regulator2 VG Series Pass Regulator3 CLKIN VB
PGND2 SREGI1
SREGO1 SREGI2 SREGO2 SREG2G SREGI3 SREGO3 C1L
CPoff VB VO1 VG VG Step-Up DC/DC Convertor VG EXT gate On Buffer VREF On EXT_G_ON SWG PGND3
VG_select VG_duty REF2 REF1 REF4 REF5
REF3 REF DAC
Figure 2. MPC18730 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data Freescale Semiconductor
TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
SREGO1
SREGI1
SREG2G
SREGO2
SEQSEL
SREGC1
SREGI2
SLEEP
SCKIN
CLKIN
STRB
DATA
VREF
WDT
GND
CLR WAKE4B WAKE3B WAKE2B WAKE1B LSWO LVB HVB V_STBY VO1 VCC1 VI1 SW1 SW1 PGND1 PGND1
1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 2 48 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
INM1 VB VGSEL2 VGSEL1 INM2 RF1 DTC1 RF2 CRST1 RSTO1B RST1ADJ PGND3 DTC2 C1L SWG VG
49 SREGC2
SREGI3 SREGO3 SREGC3 EXT_G_ON DW_2B DW_2T VO2 VO2IN VCC2 VI2 SW2 SW2 PGND2 PGND2 RSTO2B
47 46 45 44 43 42 41
TOP VIEW
40 39 38 37 36 35 34
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
33 CRST2
Figure 3. MPC18730 Terminal Connections Table 1. MPC18730 Terminal Definitions A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 14.
Terminal Number 1 2 3 4 5 6 7 8 9 Terminal Name CLR WAKE4B WAKE3B WAKE2B WAKE1B LSWO LVB HVB V_STBY Terminal Function Input Input Input Input Input Output Input Input Output Formal Name Clear Wake Signal 4 Wake Signal 3 Wake Signal 2 Wake Signal 1 Low-Side Switch Output Low Voltage Battery High Voltage Battery Standby Voltage Definition Start-up Signal Input Latch/Clear Start-up Signal Input 4 Start-up Signal Input 3 Start-up Signal Input 2 Start-up Signal Input 1 Low-Side Switch Output Terminal VB Power Supply Connection for Ni_mh VB Power Supply Connection for Li_ion V_STBY Voltage Output
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TERMINAL CONNECTIONS
Table 1. MPC18730 Terminal Definitions (continued) A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 14.
Terminal Number 10 11 12 13 14 15 16 17 Terminal Name VO1 VCC1 VI1 SW1 SW1 PGND1 PGND1 RSTO1B Terminal Function Input Output Output Power Power Ground Ground Output Formal Name Voltage Input 1 Voltage Output 1 Voltage Output 1 Switching 1 Switching 1 Power Ground 1 Power Ground 1 Inverted Reset Output 1 18 CRST1 Input Reset Delay Capacitor 1 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 RST1ADJ DTC1 RF1 INM1 C1L VG SWG PGND3 VB VGSEL2 VGSEL1 INM2 RF2 DTC2 CRST2 Output Power Output Input Power Output Power Ground Power Output Output Input Output Power Input Reset1 Adjustment Duty Control Switching Power Supply Circuit 1 Reset Voltage Reference Output Switching Power Supply Circuit 1 Maximum Duty Setting Reset Circuit 1 Reset Signal Delaying Capacitor Connection Definition Switching Power Supply Circuit 1, VO1 Voltage Input, VO1 Power Supply Power Switch 1 Output Switching Power Supply Circuit 1 Output Switching Power Supply Circuit 1 Coil Connection Switching Power Supply Circuit 1 Coil Connection Switching Power Supply Circuit 1 Power GND Switching Power Supply Circuit 1 Power GND Reset Circuit 1 Reset Signal Output
Reference Feedback 1 Switching Power Supply Circuit 1 Error Amp Output Input Minus 1 Charge Pump Capacitor Gate Voltage Switching Power Ground 3 Battery Voltage VG Select 2 VG Select 1 Input Minus Switching Power Supply Circuit 1 Error Amp Inverse Input VG Power Supply Circuit Charge Pump Capacitor Connection VG Power Supply Circuit Voltage Output, Pre-Diver Circuit Power Supply VG Power Supply Circuit Coil Connection VG Power Supply Circuit Power GND VB Power Supply Connection VG Power Supply Circuit Output Voltage Setting 2 VG Power Supply Circuit Output Voltage Setting 1 Switching Power Supply Circuit 2 Error Amp Inverting Input
Reference Feedback 2 Switching Power Supply Circuit 2 Error Amp Output Duty Control Reset Delay Capacitor 1 Switching Power Supply Circuit 2 Maximum Duty Setting Reset Circuit 2 Reset Signal Delay Capacitor Connection
34
RSTO2B
Output
Inverted Reset Output 2
Reset Circuit 2 Reset Signal Output
35 36 37 38 39 40 41 42
PGND2 PGND2 SW2 SW2 VI2 VCC2 VO2IN VO2
Ground Ground Power Power Output Output Input Input
Power Ground 2 Power Ground 2 Switching Switching Voltage Output Voltage Output Voltage Input Voltage Input
Switching Power Supply Circuit 2 Power GND Switching Power Supply Circuit 2 Power GND Switching Power Supply Circuit 2 Coil Connection Switching Power Supply Circuit 2 Coil Connection Switching Power Supply Circuit 2 Output Power Switch 2 Output Power Switch 2 Voltage Input Switching Power Supply Circuit 2 VO2 Voltage Input
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TERMINAL CONNECTIONS
Table 1. MPC18730 Terminal Definitions (continued) A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 14.
Terminal Number 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Terminal Name DW_2T DW_2B EXT_G_ON SREGC3 SREGO3 SREGI3 SREGC2 SREG2G SREGO2 SREGI2 SREGC1 SREGO1 SREGI1 GND VREF DATA STRB SCKIN WDT SEQSEL CLKIN SLEEP Terminal Function Output Output Output Power Output Power Power Output Output Power Power Output Power Ground Output Input Input Input Input Input Input Input Formal Name Step Down Top FET 2 Step Down Bottom FET 2 Gate Switch Regulator Capacitor 3 Regulator Output 3 Regulator Input 3 Regulator Capacitor 2 Regulator Gate Output 2 Regulator Output 2 Regulator Input 2 Regulator Capacitor 1 Regulator Output 1 Regulator Input 1 Ground Reference Voltage Data Signal Strobe Serial Clock Watch Dog Timer Sequence Input Clock Input Sleep Signal Definition Switching Power Supply Circuit 2 Step down Top side FET Gate Output for Ni_mh Switching Power Supply Circuit 2 Step down Bottom side FRT Gate Output for Ni_mh External Transistor Gate Signal Output Series Pass Power Supply Circuit 3 External Feedback Connection Series Pass Power Supply Circuit 3 Output Series Pass Power Supply Circuit 3 Power Supply Series Pass Power Supply Circuit 2 External Feedback Connection Series Pass Power Supply Circuit 2 External Transistor Gate Signal Output Series Pass Power Supply Circuit 2 Output Series Pass Power Supply Circuit 2 Power Supply Series Pass Power Supply Circuit 1 External Feedback Connection Series Pass Power Supply Circuit 1 Output Series Pass Power Supply Circuit 1 Power Supply GND Reference Voltage Output Serial Interface Data Signal Input Serial Interface Strobe Signal Input Serial Interface Clock Signal Input Watchdog Timer Capacitor Connection Start-Up Sequence Setting Input External Synchronous Clock Signal Input Sleep Signal Input
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MAXIMUM RATINGS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS Power Supply Voltage Analog Signal Input Logic Signal Input WAKE1~4B CLR, SLEEP, CLKIN, SCKIN, DATA, STRB VGSEL1,2 Output Power Current VCC1 Power Supply Circuit (2) VCC2 Power Supply Circuit SREG1 Power Supply Circuit SREG2 Power Supply Circuit SREG3 Power Supply Circuit VG Power Supply Circuit RSTO1B Power Supply Circuit Open-Drain Output Apply Voltage RSTO1B LSWO ESD Voltage Human Body Model (HBM) (3) Machine Model (MM) (4) Charge Device Model (CDM) THERMAL RATINGS Operating Temperature Ambient Junction Storage Temperature Thermal Resistance
(5) (1)
Symbol
Value
Unit
VB VINAN VILRSTB VILGC VILGSEL IOVO1 IOVO2 IOREG1 IOREG2 IOREG3 IOVG IORSTB VIODR VIODV VESD1 VESD2 VCDM
-0.5 to 5.0 -0.5 to VO1+0.5
V V V
-0.5 to V_STBY+0.5 -0.5 to VO1+0.5 -0.5 to VB+0.5 mA 120 100 80 100 80 8 -20 V -0.5 to 3.3 -0.5 to 3.3 V 1500 200 750
C TA TJ TSTG RJA TSOLDER -10 to 65 150 -50 to 150 69 C
C/W
C
Junction to Ambient Lead Soldering Temperature(6) 260
Notes 1. VREF, DTC1, DTC2, SREGC1, SREGC2, SREGC3 and RST1ADJ. 2. Includes the series pass power supply circuit output current. 3. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ). 4. 5. 6. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ) and in accordance with the system module specification with a capacitor 0.01 F connected from OUT to GND. Device mounted on a 2s2p test board, in accordance with JEDEC JESD51-6 and JESD51-7. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device.
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STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions VB = 1.2 V, VO1 = 2.4 V, VG = 6.0 V, fCLK = 176.4 kHz unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 27C under nominal conditions unless otherwise noted.
Characteristic GENERAL VB Power Supply Voltage Power Supply Voltage 1 Power Supply Voltage 2 Series Regulator Input Voltage (7), (8) Start-Up Voltage Analog Signal Input Logic Signal Input RSTO1 ~ 4B CLR, SLEEP, CLKIN, DATA, STRB and SCKIN VGSEL1, 2 Output Power Current VCC1 Power Supply Circuit (11) VCC2 Power Supply Circuit (11) SREG1 Power Supply Circuit SREG2 Power Supply Circuit SREG3 Power Supply Circuit VG Power Supply Circuit RSTO Supply Current in Stand-by mode VB Supply Current (VB = 1.2 V for Ni_MH) (HVB = 3.5 V for Li-Ion) Supply Current in Operating mode VB Supply Current (VB = 1.2 V for Ni_MH) (HVB = 3.5 V for Li-Ion) Reference Power Supply Circuit Output Voltage Output Current Switching Power Supply 1 VCC1 Output Voltage (Io = 0~100 mA) Notes 7. 8. 9. 10. 11. When applying voltage from an external source. 0.3 V when VG is 4.5 V. Provide 2 V or higher for the voltage difference (VG - VO1). VREF, DTC1, DTC2, SREGC1, SREGC2, SREGC3 and RST1ADJ. Includes the series pass power supply circuit output current. VREF IOREF VCC1 1.255 -0.3 2.3 1.275 2.4 1.295 0.3 2.5 V mA V IBNi IBLi 9 7 18 14 IBSNi IBSLi 5 8 10 12 mA mA IOVCC1 IOVCC2 IOSREG1 IOSREG2 IOSREG3 IOVG IORSTB 0 0 5 6 5 0 -5 100 80 60 80 60 6 0 VILRSTB VILGC VILGSEL 0 0 0 V_STBY VO1 VB mA
(10)
Symbol
Min
Typ
Max
Unit
V VLVB VHVB VSREGI VBST VIANA 0.9 2.7 VSREG+0.2 0.9 0
(9)
1.2 3.5 VSREG+0.3 -
2.2 4.2 VSREG+0.4 VO1 V V V V
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STATIC ELECTRICAL CHARACTERISTICS
This paragraph is boilerplate - you may add to it but, can not change wording. You may change numeric values
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions VB = 1.2 V, VO1 = 2.4 V, VG = 6.0 V, fCLK = 176.4 kHz unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 27C under nominal conditions unless otherwise noted.
Characteristic Switching Power Supply 2 VCC2 Output Voltage (Io = 0~80 mA) DW_2T Output Voltage (12) (Isource = 400 A) (Isink = 400 A) DW_2B Output Voltage (12) (Isource = 400 A) (Isink = 400 A) Series Pass Power Supply Circuit SREG1 Control Voltage (Io = 5~60 mA) (13) SREG1-Error AMP Input offset voltage (14) SREG2 Control Voltage (Io = 6~80 mA) (13) SREG2-Error AMP Input offset voltage (15) SREG3 Control Voltage (Io = 5~60 mA) (13) SREG3-Error AMP Input offset voltage (16) SREG2G Output Voltage (17) (Isource = 2.5 A) (Isink = 2.5 A) Power Switch On Resistance VCC1 Circuit VCC2 Circuit VG Power Supply Circuit (Io = 0~6 mA) (18) (Io = 0~6 mA) (19) C1L Output Voltage (Isource = 2.5 mA) (Isink = 2.5 mA) VGH Voltage (Certified value) V_STBY Output Voltage for Li_ion (Io = 300 A)
(20)
Symbol
Min
Typ
Max
Unit V
VCC2 VDW2TH VDW2TL VDW2BH VDW2BL VSREG1 SR1OFST VSREG2 SR2OFST VSREG3 SR3OFST SREG2GH SREG2GL RVCC1 RVCC2 VG_00 VG_10 VO11LH VO11LL VGH VLVB
1.05 5.2 0 5.2 0 2.7 -13.5 2.7 -17 2.7 -11 5 0 5.5 4.6 VB x 0.85 0 1.75
1.15 2.8 2.8 2.8 0.4 0.4 6.0 5.0 -
1.25 VG 0.3 VG 0.3 2.9 24.5 2.9 17 2.9 23 VG 0.5 0.6 0.6 V 6.5 5.4 VB 0.4 10.5 2.45 V V mV V mV V mV V V
Notes 12. Connect a transistor with gate capacity of 200 pF or smaller to DW_2T and DW_2B 13. If a capacitor with capacitance of 22F is connected to SREGO, use a phase compensation capacitor between SREGO and SREGC when the load is 5 mA (6 mA for SREG2) or lower. The output voltage values shown in the table assume that external resistance is connected as follows: SREGI1 = 3.0V to 3.3V, 65.14K between SREGO1 and SREGC1, 34.86K between SREGC1 and GND. SREGI2 = 3.0V to 3.3V, 54.46K between SREGO2 and SREGC2, 45.54K between SREGC2 and GND. SREGI3 = 3.0V to 3.3V, 73.84K between SREGO3 and SREGC3, 26.16K between SREGC3 and GND. 14. Calculated by the right formula for input offset: SR1OFST=(Vref x 0.77) - (SREGO1 / (100k / 34.86k)) 15. Calculated by the right formula for input offset: SR2OFST=(Vref x 1) - (SREGO1 / (100k / 45.54k)) 16. Calculated by the right formula for input offset: SR3OFST=(Vref x 0.58) - (SREGO1 / (100k / 26.16k)) 17. Connect a transistor with gate capacity of 300 pF or smaller to REG2G. 18. When VGSEL1 is Low and VGSEL2 is Low, I/O=3mA or higher is certified by specification. 19. When VGSEL1 is High and VGSEL2 is Low, I/O=3mA or higher is certified by specification. 20. When HVB is 4.2V and the load from V_STBY is 0.5A or higher.
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STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions VB = 1.2 V, VO1 = 2.4 V, VG = 6.0 V, fCLK = 176.4 kHz unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 27C under nominal conditions unless otherwise noted.
Characteristic Reset Circuit Reset Voltage 1 Reset Voltage 2 Hysteresis Voltage 1 (@RST1) Hysteresis Voltage 2 (@RST2) RSTB (VRSTB = 2.4 V) (Isink = 2 mA) CRST (Isink = 100 A) High Level Threshold Voltage Low Level Threshold Voltage CRST Pull-Up Resistance V_STBY Output Resistance Output Resistance (VO1) Output Resistance (VB) LSWO Output Resistance Output Resistance Ext_G_ON Ext_G_ON Output Voltage (Isource = 100 A) (Isink = 100 A) Logic Input "H" Level Input Voltage (21) "L" Level Input Voltage (21) "H" Level Input Voltage (22) "L" Level Input Voltage (22) "H" Level Input Voltage (23) "L" Level Input Voltage (23) "H" Level Input Current (21), (23) "L" Level Input Current (23), (24) Pull Up Resistance (25) Pull Down Resistance (26) Notes 21. 22. 23. 24. 25. 26. VIHVS VILVS VIH VIL VIHVB VILVB IIH IIL RPUP RPDW V_STBY - 0.2 1.5 VB - 0.2 -1 -1 410 330 590 480 0.2 0.4 0.2 1 1 770 625 V V V V V V A A K K VOHEXTG VOLEXTG VG x 0.9 0 VG VG x 0.1 V RVO1 RVB RLSWO 30 200 42 45 400 50 VRST1 VRST2 VHYRS1 VHYRS2 IORSTB1,2 VOLRSTB1,2 VOLCR1,2 VIHCR1,2 VILCR1,2 RPUPRC1,2 0.85 x VO1 0.80 x VO2 40 50 0 0 0 1.25 0.75 50 0.88 x VO1 0.85 x VO2 78 75 1.42 1.00 100 0.91 x VO1 0.90 x VO2 115 100 10 0.5 0.7 1.65 1.15 150 V V mV mV A V V V V K Symbol Min Typ Max Unit
Applied to WAKEB1 ~ 4 and SEQSEL. Applied to CLR, SLEEP, CLKIN, DATA, STRB and SCKIN. Applied to VGSEL1 and 2. Applied to WAKEB1 ~ 3, CLR, SLEEP, CLKIN, DATA, STRB, SCKIN and SEQSEL. Applied to WAKEB4. Applied to CLR, SLEEP, CLKIN, DATA, STRB and SCKIN.
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DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions VB = 1.2 V, VO1 = 2.4 V, VG = 6.0 V, fCLK = 176.4 kHz unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 27C under nominal conditions unless otherwise noted.
Characteristic OSCILLATOR Internal Oscillation Frequency MICRO CONTROLLER INTERFACE Clock Signal Input (27) Serial Interface (Refer to Timing Chart below) DATA Set Up Time DATA Hold Time SCKIN Clock Frequency SCKIN 'H' Pulse Width SCKIN 'L' Pulse Width SCKIN Hold Time STRB Set Up Time STRB Pulse Width Notes 27. Duty 50%. ts th fsck twckh twckl thck tssb twsb 20 20 50 50 50 50 50 6.0 nsec nsec MHz nsec nsec nsec nsec nsec fCLK 176.4 kHz fICK 150 200 250 kHz Symbol Min Typ Max Unit
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DIAGRAMS
FUNCTIONAL DIAGRAMS
WAKE1~4(int)
CLKIN
INT
VO1
EXT (Serial setting)
V_STBY
VB
VB
VB
VB VG
VG
VB VO1
VB
RSTO1B(Int)
VO1
CRST set value
RSTO1B
VO1
VO1
VB*1 VO1
VB*1
VCC1
VO2
VO2
VO2
VCC2
VO1
RSTO2B(Int)
CRST set value
VO1
RSTO2B
VSREG1~3
SEQSEL setting
DATA
DATA
STRB
SEQSEL setting
CLR
SLEEP Standby Mode Start-Up *1: When using Ni_mh. High-Z when using Li_ion. Operation Mode Standby Mode
Figure 4. Power Supply Start-Up Timing Diagram
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FUNCTIONAL DIAGRAMS
tssb SCKIN ts DATA
twckh
twckl
thck
th A3 A2 D0 twsb
STRB
Figure 5. Serial Interface Timing Diagrams
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DIAGRAMS
Table 5. Serial Interface Functions
Register Name Address 0 1 2 3 4 5 6 7 CLR, SLEEP Power Mode Clock Select VO1 VO2 SREG1 SREG2 SREG3 1000 0001 0010 0011 0100 0101 0110 0111 CLR PSW1 Ext / Int MSB MSB MSB MSB MSB DATA1 SLEEP PSW2 Half Freq Reserved RSTO1B RSTB sleep Reserved VCC2 S_Off_VG Reserved SREG1 VG_Duty[3] DATA2 Reserved SREG2 VG_Duty[2] Reserved SREG3 VG_Duty[1] LSB LSB LSB Reserved RSTO2B VG_Duty[0] S_Off_VO1 S_Off_VO2 Reserved LSB LSB CP Off EXTG On
VO1 Output Voltage VO2 Output Voltage SREG1 Output Voltage SREG2 Output Voltage SREG3 Output Voltage
Twelve bits immediately before start-up of STRB are always effective. Upon power on, the internal power on reset works to initialize the registers. Serial data is fetched in the Table 6. Block Operation
INPUT WAKE(Int) L H H H H H RSTO1B(Int) X L H H H H RSTO1B X L L L H H RSTO2B(Int) X L L L H H
order of Add_[3], Add_[2], ..., Add_[0], DATA1_[3], DATA1_[2], ...., DATA2_[0].
OUTPUT SEQSEL X L L H L H VG O O O O O VO1 O O O O O VO2 O O VCC1,2 O O REG1,2,3 O O O
O : Operation, - : Stop, X : Don't care
Table 7. Start-Up Sequence Settings
SEQSEL V_STBY GND CLR/SLEEP RSTO2B(Ext) RSTO1B(Ext) Series Regulators RSTO2B(Int) RSTO1B(Int)
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 18730 power management integrated circuit provides five independent output voltages for the micro controller from either a single cell Li-Ion or from a single cell Ni-MH or dry cell. The PMIC includes two DC to DC converters and three low drop out linear regulators. The output voltage for each of the five output voltages is set independently through a 3-wire serial interface. The PMIC has multiple wakeup, sleep, and reset modes to minimize power consumption for portable equipment. In single cell Li-Ion applications two DC-DC converters are configured as buck regulators. In single cell Ni-MH or dry cell applications, one DC-DC converter is configured as a boost regulator, and the other as buck-boost regulator.
FUNCTIONAL TERMINAL DESCRIPTION CLEAR TERMINAL (CLR)
This Clear input signal makes clear internal latches for WAKE signal holding. The WAKE control circuit can not receive another WAKE input until the latch is cleared by this Clear input.
VOLTAGE OUTPUT TERMINALS (VCC1, VCC2)
Output `VO1' or `VO2' voltage controlled internal power switch.
POWER INPUT TERMINALS (VI1, VI2)
The power input terminals (VI1, VI2) are drain terminals on the top side FET of the DC/DC converter switcher. They are the power input for the buck converter and output for the boost converter.
WAKE SIGNAL TERMINALS (WAKE1B, WAKE2B, WAKE3B, WAKE4B) ... ACTIVE LOW
Any one WAKE input signal of these four WAKE inputs awakes this device from sleep mode. The WAKE signals can be made with external low side mechanical switch and resistance that is pulled up to VSTB rail.
SWITCHING TERMINALS (SW1, SW2)
Switching Terminals (SW1, SW2) are the output of the half bridge and connect to the external inductance.
LOW-SIDE SWITCH OUTPUT TERMINAL (LSWO)
Low-Side switch output that is turned on with `CLR' signal. It can be used for external key input latches clear.
POWER GROUND TERMINALS (PGND1, PGND2, PGND3)
Ground level node for DC/DC converter and Charge Pump portion.
LOW VOLTAGE BATTERY TERMINAL (LVB)
This input terminal is used for temporarily power supply while wake up for 1cell Ni-MH battery or 1cell dry cell battery (= Low Voltage Battery) use. It has to be connected to VB rail. When Li-Ion battery is used, the terminal has to be open.
INVERTED RESET OUTPUT TERMINALS (RSTO1B, RSTO2B)
Reset signal output for external MPU or the something controller. RSTO1B keeps `Low' level while the VO1 voltage is less than internal reference voltage. RSTO2B follows to VO2 voltage.
HIGH VOLTAGE BATTERY TERMINAL (HVB)
This input terminal is used for temporarily power supply while wake up for Li-Ion battery (= High Voltage Battery) use. It has to be connected to the VB rail. When a Ni-MH battery is used, the terminal has to be connected to ground level.
RESET DELAY CAPACITOR TERMINALS (CRST1, CSRT2)
The capacitor which is connected to this terminal decide delay time to negate Reset signal from exceeding the reference voltage level.
STANDBY VOLTAGE TERMINAL (V_STBY)
Standby Voltage is made from LVB or HVB that depends on which battery is used. This voltage is used for internal logic and analog circuit at standby (sleep) mode temporarily before `VO1' voltage is established.
RESET 1 ADJUSTMENT TERMINAL (RST1ADJ)
Used to adjust the reset level with external resistance which is connected to VO1 for RSTO1B.
VOLTAGE INPUT TERMINALS (VO1, VO2)
This power supply input terminal named `VO1 or VO2' is for internal logic and analog circuits and for input of `VCC1' output via power switch. Input for `VCC2' is `VO2IN' terminal. It is supplied from the output of Channel-1 or Channel-2 DC/ DC converter as `VO1 or VO2.
18730
DUTY CONTROL TERMINALS (DTC1, DTC2)
Connected external voltage to this terminal via capacitance can control the duty of DC/DC converter switching. Use of the terminal for this is not recommended.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION
REFERENCE FEEDBACK TERMINALS (RF1, RF2)
Output node of internal error amp. for DC/DC converter 1 and 2. For phase compensation use.
Input the feed back voltage that divided SREGO voltage by resistances.
INPUT MINUS TERMINALS (INM1, INM2)
Minus input of internal error amp. for DC/DC converter 1 and 2. For phase compensation use.
REGULATOR OUTPUT TERMINALS (SREGO1, SREGO2, SREGO3)
Series regulator output terminals. All output voltages can be variable with internal DAC via serial I/F.
CHARGE PUMP CAPACITOR TERMINAL (C1L)
In case of use higher voltage than VG externally, connect capacitance and diodes between VG. The charge pump structure can output VG + VB - 2 x VF voltage. There is no meaning for Ni-MH or dry cell battery, because the VB voltage is almost same as 2 x VF voltage. Recommend to use for Li-Ion battery use.
REGULATOR INPUT TERMINALS (SREGI1, SREGI2, SREGI3)
Series regulator power input terminals. To be connected to battery voltage in general.
GROUND TERMINAL (GND)
Ground terminal for logic and analog circuit portion (not power portion). Recommend to connect to clean ground which separated with power ground line.
GATE VOLTAGE TERMINAL (VG)
Output terminal of boost converter for gate drive voltage. The output voltage is decided by VGSEL input.
REFERENCE VOLTAGE TERMINAL (VREF)
Output of internal reference voltage. It can be used externally. Output current capacity is less than 300uA.
SWITCHING FOR GATE VOLTAGE TERMINAL (SWG)
Switching terminal for VG boost converter. Connect to external inductance.
DATA INPUT TERMINAL (DATA)
Serial data input terminal. The latest 12 bits before strobe signal are valid.
BATTERY VOLTAGE TERMINAL (VB)
Power supply input that connects to Ni-MH or Dry cell or Li-Ion battery.
STROBE TERMINAL (STRB)
Strobe signal input terminal for serial I/F. It establishes the input 12bits data to internal control registers.
VG SELECT TERMINALS (VGSEL1, VGSEL2)
VG output voltage is decided with these two bits input.
SERIAL CLOCK TERMINAL (SCKIN)
Clock input terminal for serial I/F. Input data are taken in to I/F with this clock.
VOLTAGE INPUT FOR POWER SWITCH 2 TERMINAL (VO2IN)
Input of VCC2 output via power switch. Connect to VO2 terminal externally.
WATCH DOG TIMER TERMINAL (WDT)
Watch dog timer prevent unstable wake up (flips between wake-up and failure). If there is no `CLR' input after any WAKEnB input before this WDT is expired, this device move to `SLEEP' mode to prevent wake failure hanging-up situation.
STEP DOWN FET GATE DRIVE TERMINALS (DW_2T, DW_2B)
Gate drive output terminals for external FETs to use DC/ DC converter 2 as Buck / Boost converter.
SEQUENCE SELECT TERMINAL (SEQSEL)
Select judgement Reset channel for wake-up complete with this input. If this input level is VSTB voltage, this device judges the wake-up completion with Reset2 (DC/DC2). If it is Ground, judge with Reset1 (DC/DC1). See Table 7, on page 13.
GATE SWITCH TERMINAL (EXT_G_ON)
Gate drive output terminal for external low side switch. It can be used for power switch turning On/OFF for remote controller part.
REGULATOR CONTROL TERMINALS (SREGC1, SREGC2, SREGC3)
Feed back terminal for each series regulators. This terminal voltage is compared with internal reference voltage.
CLOCK INPUT TERMINAL (CLKIN)
Clock input terminal for internal switching part. This device has a oscillator internally, but can be used this input clock for internal switching frequency. It is selected by Clock select bit. See Table 19, on page 26.
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FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION
SLEEP MODE TERMINAL (SLEEP)
The sleep input signal puts the device in sleep mode. All output voltages are down, and internal current consumption will be minimum.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES START-UP CONTROL INPUT (SYSTEM CONTROL)
The latch is set at the rising edge of any WAKE1B-4B input pin, and WAKE(int) goes High. WAKE1~4B inputs consist of OR logic. At this time, the input pin which went Low keeps latched until CLR goes High. After the latch is reset by CLR, WAKE(int) goes Low when SLEEP goes High. The latch is also cleared and WAKE(int) goes Low when SLEEP goes High before the latch is cleared by CLR. In this case, CLR keeps negated while RSTO1B, 2B(Ext) is Low. SLEEP keeps negated while RSTO1B, 2B(Ext) is Low or CLR is High. The period of time for which CLR and SLEEP are negated can be set by the SEQSEL pin. Refer to Truth Table 5, on page 13 for the correspondence between the SEQSEL pin settings and negation period. If SLEEP goes High to place the chip into the standby mode while any of the WAKEB pins is Low, the chip can be awakened again. This may happen if, when an WAKEB pin and LSWO are connected, SLEEP goes High earlier than the period of time (*1) specified by the external component of the WAKEB pin. Also, if the period of time after WAKE(int) goes High until CLR goes High from Low is longer than the time specified by WDT, internal sleep will start up to place the chip into the standby mode. (*1: It is 30 sec when a capacitor is not connected as the external component.)
WAKEB
CLR Time specified by WDT WDT
WAKE(Int)
Figure 6. Start-Up Timing Diagram
STANDBY POWER SUPPLY CIRCUIT
LSWO CLR VB HVB RST1B VO1 Short-circuit VB and LVB, and connect a Schottky diode between VB and V_STBY only when using Ni_mh. VB LVB V_STBY V_STBY When using Li_ion, leave LVB open, and shortcircuit HVB and VB.
Standby Power RST1B(Int) Supply Control
Figure 7. Standby Power Supply Circuit Diagram
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
When RSTO1B(int) is Low, output LVB voltage to V_STBY terminal. When RSTO1B(int) is High, output VO1 voltage to V_STBY terminal. When CLR is Low, LSWO is open. When RSTO1B(int) is High and CLR is High, LSWO output voltage turns GND. When RSTO1B(int) is Low and RSTO1B is High, discharge the external capacitor which is connected to
V_STBY. When using Ni_mh, short-circuit VB and LVB to external components and HVB to GND. When using Li_ion, short-circuit HVB to VB, and leave LVB open. When using Ni_MH, the VB voltage is output from V_STBY in Standby mode. When using Li-Ion, 50% of the VB voltage is output to V_STBY terminal in Standby Mode.
Table 8. HVB and LVB Connection
MODE Li_ion Ni_mh HVB VB(28) GND LVB open VB(28)
Notes 28. Externally connect to VB.
Table 9. V_STBY and LSWO Operation
INPUT WAKE(Int) L H H H RSTO1B(Int) X L H H CLR X X L H OUTPUT V_STBY VB VB VO1 VO1 LSWO Z Z Z L
Z : High Impedance, X : Don't care
RESET CIRCUIT
VO1 VO1, 2 VG
CRST1, 2 RST1B, 2B
RST1ADJ (RSTO1B side only)
VO1
Reset Control RSTO1B, 2B(Int)
CRST1, 2
BANDGAP REFERENCE
Figure 8. Reset Circuit Block Diagram When the VO1 or VO2 voltage is higher than the reference value, RSTO1B or 2B goes High. When RSTO1B(int) is Low and RSTO1B is High, SLEEP(int) is forced to place the chip into the standby mode. Connect a capacitor between RST1ADJ and CRST. The capacitor is not necessary if a resistor of 330K or less is inserted between RST1ADJ and VC1 for reset adjustment Connect the capacitor between RST1ADJ and RSTB as directed below. When SEQSEL is Low: Between RST1ADJ and CRST1 When SEQSEL is High: Between RST1ADJ and CRST2 Use a capacitor with approximately half of the capacitance between CRST and GND
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
RST1B(Int)
RST1B
SLEEP(Int)
Figure 9. Reset Timing Diagram
POWER SUPPLY VO1, VO2: NI_MH
The VB voltage rises and is output to VI1. When RSTO2B(int) is High, the power switch turns ON to output the VO1 voltage to VCC1. Capacitance value which is connected to VO1 should be higher than the capacitor connected to VCC1. Table 10. Output Voltage of VO1
Address : 0011(30) B7 L L L L L L L H H H H H H H H B6 L L L L L L H L L L L L L H H B5 L L L L L H L L L L L L H L H B4 L L L L H L L L L L L H L L H B3 L L L H L L L L L L H L L L H
The VB voltage rises or falls and is output to VI2. When RSTO2B(int) is High, the power switch turns ON to output the VO2IN voltage to VCC2. If you turn DDC2 OFF using the register, the power switch 2 also turns OFF. Capacitance value which is connected to VO2IN should be higher than the capacitor connected to VCC2.
B2 L L H L L L L L L H L L L L H
B1 L H L L L L L L H L L L L L H
S_Off_VO1 X X X X X X X X X X X X X X X
VO1 [V](29) 1.613 1.625 1.638 1.663 1.713 1.813 2.013 2.413 2.425 2.438 2.463 2.513 2.613 2.813 3.200
Notes 29. Operation is not guaranteed when VO1 input voltage is 1.8 V or lower. By connecting a diode between VI1 and VO1, VI1 can output voltage higher (with the voltage difference Vf) than VO1. 30. All combinations of input are not included.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Table 11. Output Voltage of VO2
Address : 0100(31) B7 L L L L L L L H H H H H H H H B6 L L L L L L H L L L L L L H H B5 L L L L L H L L L L L L H L H B4 L L L L H L L L L L L H L L H B3 L L L H L L L L L L H L L L H B2 L L H L L L L L L H L L L L H B1 L H L L L L L L H L L L L L H S_Off_VO2 X X X X X X X X X X X X X X X VO2 [V] 0.805 0.811 0.816 0.827 0.849 0.893 0.980 1.155 1.161 1.166 1.177 1.199 1.243 1.330 1.500
Notes 31. All combinations of input are not included.
POWER SUPPLY VO1, VO2: LI-ION
The VB voltage falls and is output to VO1. When using Li_ion, duty limit due to DTC1 is not applied to the switch. When RSTO2B(int) is High, the power switch turns ON to output the VO1 voltage to VCC1. Capacitance value which is connected to VO1 should be higher than the capacitor connected to VCC1.
The VB voltage falls using only the internal transistor and is output to VO2. When using Li_ion, duty limit due to DTC2 is not applied to the switch, and DW_2T and DW_2B are Low. When RSTO2B(int) is High, the power switch turns ON to output the VO2IN voltage to VCC2. If you turn DDC2 OFF using the register, the power switch 2 also turns OFF. Capacitance value which is connected to VO2IN should be higher than the capacitor connected to VCC2.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
SERIES PASS POWER SUPPLY
The series pass outputs the SREGI1 voltage to SREGO1, the SREGI2 voltage to SREGO2, and the SREGI3 voltage to Table 12. Output Voltage of SREG1
Address : 0101(31) B7 L L L L L L L H H H H H H H H B6 L L L L L L H L L L L L L H H B5 L L L L L H L L L L L L H L H B4 L L L L H L L L L L L H L L H B3 L L L H L L L L L L H L L L H
SREGO3. If you use MOSFET as the external component in this case, connect the gate to SREG2G.
B2 L L H L L L L L L H L L L L H
B1 L H L L L L L L H L L L L L H
Reserved H H H H H H H H H H H H H H H
SREG1 [V](32) 0.865 0.880 0.895 0.926 0.986 1.107 1.349 1.833 1.848 1.863 1.893 1.954 2.075 2.317 2.800
Notes 32. The SREG1 and 3 output voltages are determined by the combination of external resistances connected to REGC1 and 3 (65.14K between SREGO1 and REGC1, 34.86K between REGC1 and GND, 73.84K between SREGO3 and REGC3, and 26.16K between REGC3 and GND). 33. All combinations of input are not included.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Table 13. Output Voltage of SREG2
Address : 0110(31) B7 L L L L L L L L H H H H H H H H H B6 L L L L L L L H L L L L L L L H H B5 L L L L L L H L L L L L L L H L H B4 L L L L L H L L L L L L L H L L H B3 L L L L H L L L L L L L H L L L H B2 L L L H L L L L L L L H L L L L H B1 L L H L L L L L L L H L L L L L H B0 L H L L L L L L L H L L L L L L H SREG2 [V] 0.011 0.022 0.033 0.055 0.098 0.186 0.361 0.711 1.411 1.422 1.433 1.455 1.498 1.586 1.761 2.111 2.800
Notes 34. All combinations of input are not included.
Table 14. Output Voltage of SREG3
Address : 0111(31) B7 L L L L L L H H H H H H H B6 L L L L L H L L L L L H H B5 L L L L H L L L L L H L H B4 L L L H L L L L L H L L H B3 L L H L L L L L H L L L H B2 L H L L L L L H L L L L H CP Off X X X X X X X X X X X X X EXTG On X X X X X X X X X X X X X SREG3 [V](35) 2.080 2.091 2.102 2.125 2.170 2.260 2.440 2.451 2.462 2.485 2.530 2.620 2.800
Notes 35. The SREG1 and 3 output voltages are determined by the combination of external resistances connected to REGC1 and 3 (65.14K between SREGO1 and REGC1, 34.86K between REGC1 and GND, 73.84K between SREGO3 and REGC3, and 26.16K between REGC3 and GND). 36. All combinations of input are not included.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
VG GENERATOR
VB VG Start Up VG VG Step-Up Pre Driver LG VB VG
PGND3 VG_select VG_duty
Figure 10. Circuit when using a Step-Up Converter When WAKE (int) goes High from Low, the start-up circuit raises the VB voltage and outputs it to VG, then outputs the VG voltage when RSTO1B (int) goes High. The charge pump circuit can be used for both Ni_mh and Li_ion by setting the necessary registers. The charge pump circuit is disabled by default. The VG voltage can be set to 6 V to 4.5 V according to the combination of VGSEL1 and 2 pin connections. Refer to Table 16, VG Voltage Settings and VGSEL1 and 2 Pin Connection on page 24 for the VG voltage settings. When using a charge pump, please refer to Figure 11.
VB VB VG Start Up VG VG Step-Up Pre Driver
C1L
VGH
CPoff
VG
VG
VB LG
PGND3 VG_select VG_duty
Figure 11. Circuit When Using a Charge Pump
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Table 15. VG Duty Settings
Address : 0010 Ext/Int X X X X X X X X X Half Freq X X X X X X X X X RSTB sleep X X X X X X X X X S_Off_VG X X X X X X X X X VG_Duty[3] L L L L H H H H H VG_Duty[2] L L L H L L L H H VG_Duty[1] L L H L L L H L H VG_Duty[0] L H L L L H L L H Duty 90 % 86 % 82 % 74 % 58 % 54 % 50 % 42 % 30 %
Table 16. VG Voltage Settings and VGSEL1 and 2 Pin Connection
VGSEL1 GND GND VB VB VGSEL2 GND VB GND VB VG [V] 6.0 5.5 5.0 4.5
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS REGISTER MAPPINGS
Table 17. CLR and SLEEP Control Register
1000 Bit Name Default 3 CLR 0 2 SLEEP 0 Data1 1 Reserved 0 0 Reserved 0 3 Reserved 0 2 Reserved 0 Data2 1 Reserved 0 0 Reserved 0
CLR : CLR Control 1 = CLR is high 0 = CLR is low SLEEP : SLEEP Control 1 = SLEEP is high 0 = SLEEP is low Reserved : Freescale defined register *1 1 = Forbidden 0 = Required Reserved : Freescale defined register *1 1 = Forbidden 0 = Required Reserved : Freescale defined register *1 1 = Forbidden 0 = Required Table 18. Power Mode Register
0001 Bit Name Default 3 PSW1 1 2 PSW2 1 Data1 1 RSTO1B 0 0 VCC2 1
Reserved : Freescale defined register *1 1 = Forbidden 0 = Required Reserved : Freescale defined register *1 1 = Forbidden 0 = Required Reserved : Freescale defined register *1 1 = Forbidden 0 = Required Note : Do NOT change Reserved Register from default value. *1: Data write to this address (1000) is allowed for the most significant two bits only. The least significant 6 bits are only used for the factory test. When writing data, always write 0 to these six bits.
Data2 3 SREG1 1 2 SREG2 1 1 SREG3 1 0 RSTO2B 0
PSW1 : VCC1 Power Switch control 1 = Power Switch on 0 = Power Switch off PSW2 : VCC2 Power Switch control 1 = Power Switch on 0 = Power Switch off RSTO1B : RSTO1B Mask *1 1 = RSTO1B mask on 0 = RSTO1B mask off VO2 : DC/DC Converter Channel 2 output Control *2 1 = DDC2 on 0 = DDC2 off SREG1 : Series Pass Regulator Channel1 output Control 1 = Regulator on 0 = Regulator off
SREG2 : Series Pass Regulator Channel2 output Control *3 1 = Regulator off 0 = Regulator on SREG3 : Series Pass Regulator Channel3 output Control 1 = Regulator on 0 = Regulator off RSTO2B : RSTO2B Mask *1 1 = RSTO2B mask on 0 = RSTO2B mask off *1: When switching the output voltage of VO1 (2), write 1 to the RSTO1B (2) Mask bit in advance to fix the rest output to High for preventing erroneous operation. *2: When turning DDC2 OFF, set the RSTO2B bit to High to Mask RSTO2B. If you turn DDC2 OFF, the power switch 2 also turns OFF.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Table 19. Clock Select Register
0010 Bit Name Default 3 Ext/Int 0 2 Half Freq 0 Data1 1 RSTB sleep 1 0 S_Off_VG 0 3 VG_Duty [3] 0 2 VG_Duty[2] 0 Data2 1 VG_Duty[1] 0 0 VG_Duty[0] 0
Ext / Int : Clock Select control 1 1 = External Clock 0 = Internal Clock 2FS : Clock Select control 2 1 = 2FS on 0 = 2FS off RSTB Sleep : RSTB Sleep Monitor *1 1 = RSTB SLEEP Monitor off 0 = RSTB SLEEP Monitor on S_Off_VG : VG Top side transistor off 1 = Synchronous Rectification Off 0 = Synchronous Rectification On VG_Duty[3] : VG Duty Control MSB 1 = VG Duty[3] is high 0 = VG Duty[3] is low Table 20. VO1 Output Voltage Register
0011 Bit Name Default 3 VO1_V[6] 1 2 VO1_V[5] 0 Data1 1 VO1_V[4] 0 0
VG_Duty[2] : VG Duty Control Bit 2 1 = VG Duty[2] is high 0 = VG Duty[2] is low VG_Duty[1] : VG Duty Control Bit1 1 = VG Duty[1] is high 0 = VG Duty[1] is low VG_Duty[0] : VG Duty Control LSB 1 = VG Duty[0] is high 0 = VG Duty[0] is low VG is controlled by PFM method. This register can change the duty by 16 steps. Refer to Table 15, VG Duty Settings on page 24 for the correspondence between the VG Duty maximum values and register settings.
Data2 3 VO1_V[2] 0 2 VO1_V[1] 0 1 VO1_V[0] 0 0 S_Off_VO1 0
VO1_V[3] 0
VO1_V[6] : Reference DAC MSB 1 = VO1_V[6] on 0 = VO1_V[6] off VO1_V[5] : Reference DAC Bit5 1 = VO1_V[5] on 0 = VO1_V[5] off VO1_V[4] : Reference DAC Bit4 1 = VO1_V[4] on 0 = VO1_V[4] off VO1_V[3] : Reference DAC Bit3 1 = VO1_V[3] on 0 = VO1_V[3] off VO1_V[2] : Reference DAC Bit2 1 = VO1_V[2] on 0 = VO1_V[2] off
VO1_V[1] : Reference DAC Bit1 1 = VO1_V[1] on 0 = VO1_V[1] off VO1_V[0]: Reference DAC LSB 1 = VO1_V[0] on 0 = VO1_V[0] off S_Off_VO1 : DDC1 Top side (Ni_mh) / Bottom side (Li_ion) transistor off 1 = Synchronous Rectification Off 0 = Synchronous Rectification On Refer to Table 10, Output Voltage of VO1 on page 19 for the correspondence between the output voltage and register settings.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Table 21. VO2 Output Voltage Register
0100 Bit Name Default 3 VO2_V[6] 1 2 VO2_V[5] 0 Data1 1 VO2_V[4] 0 0 VO2_V[3] 0 3 VO2_V[2] 0 2 VO2_V[1] 0 Data2 1 VO2_V[0] 0 0 S_Off_VO2 0
VO2_V[6] : Reference DAC MSB 1 = VO2_V[6] on 0 = VO2_V[6] off VO2_V[5] : Reference DAC Bit5 1 = VO2_V[5] on 0 = VO2_V[5] off VO2_V[4] : Reference DAC Bit4 1 = VO2_V[4] on 0 = VO2_V[4] off VO2_V[3] : Reference DAC Bit3 1 = VO2_V[3] on 0 = VO2_V[3] off VO2_V[2] : Reference DAC Bit2 1 = VO2_V[2] on 0 = VO2_V[2] off Table 22. Regulator1 Output Voltage Register
0101 Bit Name Default 3 SREG1_V[6] 1 2 SREG1_V[5] 1 Data1 1 SREG1_V[4] 1 0
VO2_V[1] : Reference DAC Bit1 1 = VO2_V[1] on 0 = VO2_V[1] off VO2_V[0]: Reference DAC LSB 1 = VO2_V[0] on 0 = VO2_V[0] off S_Off_VO2 : DDC2 Top side & DW2B (Ni_mh) / Bottom side (Li_ion) transistor off 1 = Synchronous Rectification Off 0 = Synchronous Rectification On Refer to Table 11, Output Voltage of VO2 on page 20 for the correspondence between the output voltage and register settings.
Data2 3 SREG1_V[2] 1 2 SREG1_V[1] 1 1 SREG1_V[0] 1 0 Reserved 1
SREG1_V[3] 1
SREG1_V[6] : Reference DAC MSB 1 = SREG1_V[6] on 0 = SREG1_V[6] off SREG1_V[5] : Reference DAC Bit5 1 = SREG1_V[5] on 0 = SREG1_V[5] off SREG1_V[4] : Reference DAC Bit4 1 = SREG1_V[4] on 0 = SREG1_V[4] off SREG1_V[3] : Reference DAC Bit3 1 = SREG1_V[3] on 0 = SREG1_V[3] off SREG1_V[2] : Reference DAC Bit2 1 = SREG1_V[2] on 0 = SREG1_V[2] off
SREG1_V[1] : Reference DAC Bit1 1 = SREG1_V[1] on 0 = SREG1_V[1] off SREG1_V[0]: Reference DAC LSB 1 = SREG1_V[0] on 0 = SREG1_V[0] off Reserved : Blank register bit (Freescale Pre-Defined Register) 1 = Preferred 0 = Forbidden Note : Do NOT change Reserved Register from default value. Refer to Table 12, Output Voltage of SREG1 on page 21 for the correspondence between the output voltage and register settings.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Table 23. Regulator2 Output Voltage Register
0110 Bit Name Default 3 SREG2_V[7] 1 2 SREG2_V[6] 1 Data1 1 SREG2_V[5] 1 0 SREG2_V[4] 1 3 SREG2_V[3] 1 2 SREG2_V[2] 1 Data2 1 SREG2_V[1] 1 0 SREG2_V[0] 1
SREG2_V[7]: Reference DAC MSB 1 = SREG2_V[7] on 0 = SREG2_V[7] off SREG2_V[6] : Reference DAC Bit6 1 = SREG2_V[6] on 0 = SREG2_V[6] off SREG2_V[5] : Reference DAC Bit5 1 = SREG2_V[5] on 0 = SREG2_V[5] off SREG2_V[4] : Reference DAC Bit4 1 = SREG2_V[4] on 0 = SREG2_V[4] off SREG2_V[3] : Reference DAC Bit3 1 = SREG2_V[3] on 0 = SREG2_V[3] off Table 24. Regulator3 Output Voltage Register
0111 Bit Name Default 3 SREG3_V[5] 1 2 SREG3_V[4] 1 Data1 1 SREG3_V[3] 1 0
SREG2_V[2] : Reference DAC Bit2 1 = SREG2_V[2] on 0 = SREG2_V[2] off SREG2_V[1] : Reference DAC Bit1 1 = SREG2_V[1] on 0 = SREG2_V[1] off SREG2_V[0]: Reference DAC LSB 1 = SREG2_V[0] on 0 = SREG2_V[0] off Refer to Table 13, Output Voltage of SREG2 on page 22 for the correspondence between the output voltage and register settings.
Data2 3 SREG3_V[1] 1 2 SREG3_V[0] 1 1 CP Off 1 0 EXTG On 1
SREG3_V[2] 1
SREG3_V[5] : Reference DAC MSB 1 = SREG3_V[5] on 0 = SREG3_V[5] off SREG3_V[4] : Reference DAC Bit4 1 = SREG3_V[4] on 0 = SREG3_V[4] off SREG3_V[3] : Reference DAC Bit3 1 = SREG3_V[3] on 0 = SREG3_V[3] off SREG3_V[2] : Reference DAC Bit2 1 = SREG3_V[2] on 0 = SREG3_V[2] off SREG3_V[1] : Reference DAC Bit1 1 = SREG3_V[1] on 0 = SREG3_V[1] off
SREG3_V[0]: Reference DAC LSB 1 = SREG3_V[0] on 0 = SREG3_V[0] off CP Off : Charge Pump Control 1 = Charge Pump off 0 = Charge Pump on EXTG On : EXT_G_ON Control * 1 = EXT_G_ON is low (GND level) 0 = EXT_G_ON is high (VG level) EXTG On Register is assumed to use Pch FET as external MOSFET. If Nch FET will be used, Control logic should be inverted. Refer to Table 14, Output Voltage of SREG3 on page 22 for the correspondence between the output voltage and register settings.
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TYPICAL APPLICATIONS LOGIC COMMANDS AND REGISTERS
TYPICAL APPLICATIONS
HVB LVB Driver VREF LSWO VO1 RSTO1B VO1 CRST1 RST1ADJ INM1 RF1 VREF DTC1 VO1 RSTO2B CRST2 INM2 RF2 VREF DTC2 VG SREGO1 SREGC1 SREGO2 SREGC2 SREGO3 SREGC3 V_STBY WAKE1B WAKE2B WAKE3B WAKE4B SEQSEL DATA STRB SCKIN CLR SLEEP CLKIN GND REF2 VGSEL1 VGSEL2 WDT REF1 REF3 REF DAC VO1 VB REF5 RSTO1B(Int)
CONTROL
VMODE VMODE RSTO1B(Int)
VB
VB LVB
VB
VO1
VREF RSTO1B(Int) CLR VO1 RESET Block 1
VG RSTO2B(Int) POWER RSTO1B(Int) VO1 VG SWITCH1
BANDGAP REFERENCE
VO1
V_STBY VCC1 VO1 VI1 VB SW1 PGND1 VCC2 VO2IN VO2 DW_2T
VB
Step-UpDown DC/DC Converter CH1 VG RSTO2B(Int) VG RSTO2B(Int) POWER SWITCH2
CRST1 or CRST2
VO1 RESET Block 2
REF2
Step-UpDown DC/DC Converter CH2
DW_2B VI2 SW2 PGND2 SREGI1
REF3
Series Pass Regulator1 SREGO1 VG SREGI2 SREGO2 SREG2G SREGI3 SREGO3 C1L Series Pass Regulator2 VG Series Pass Regulator3 CLKIN VB
REF4
RSTO2B (Int) SEQSEL Control Logic
CPoff VB VO1 VG Step-Up DC/DC Convertor VG EXT gate On Buffer VREF On
VG VB SWG PGND3
VG_select VG_duty REF4 REF5
EXT_G_ON
Figure 12. MPC18730 Typical Application Diagram (Ni-MH Battery)
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TYPICAL APPLICATIONS LOGIC COMMANDS AND REGISTERS
VB
HVB
LVB Driver VO1
VMODE VMODE RSTO1B(Int)
VB
VB LVB
VB
VREF
VREF RSTO1B(Int) CLR VO1 RESET Block 1
VO1
BANDGAP REFERENCE
V_STBY VCC1 VO1 VB VI1 SW1 PGND1
VO1
LSWO
VG RSTO2B(Int) POWER RSTO1B(Int) VO1 VG SWITCH1 Step-UpDown DC/DC Converter CH1
RSTO1B VO1 CRST1 RST1ADJ INM1 RF1 CRST1 or CRST2
VG DTC1 VO1 RSTO2B CRST2 INM2 RF2 VO1 POWER RSTO2B(Int) SWITCH2 VG RSTO2B(Int) RESET Block 2
VCC2 VO2IN VO2 DW_2T
REF2
Step-UpDown DC/DC Converter CH2
DW_2B VB VI2 SW2
DTC2 VG SREGO1 SREGC1
SREGO2
PGND2 SREGI1
REF3
Series Pass Regulator1 VG SREGO1 SREGI2 SREGO2 SREG2G SREGI3 SREGO3 C1L VGH
SREGC2
SREGO3
REF4
SREGC3
Series Pass Regulator2 VG
V_STBY WAKE1B WAKE2B WAKE3B WAKE4B SEQSEL DATA STRB SCKIN CLR SLEEP CLKIN GND VGSEL1 VGSEL2 WDT
VO1 VB REF5 RSTO1B(Int) RSTO2B (Int) SEQSEL
Series Pass Regulator3 CLKIN VB
CONTROL
CPoff VB VO1 VG Step-Up DC/DC Convertor VG On EXT gate On Buffer
VG SWG PGND3 VB
Control Logic
VG_select VG_duty REF4 REF2 REF1 REF3 REF5 REF DAC
EXT_G_ON
VREF
Figure 13. MPC18730 Typical Application Diagram (Li-Ion Battery)
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below.
EP (Pb-FREE) SUFFIX 64-TERMINAL 0.5mm pitch PLASTIC PACKAGE 98ARL10571D ISSUE B
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Analog Integrated Circuit Device Data Freescale Semiconductor
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PACKAGING PACKAGE DIMENSIONS
EP (Pb-FREE) SUFFIX 64-TERMINAL 0.5mm pitch PLASTIC PACKAGE 98ARL10571D ISSUE B
18730
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS
EP (Pb-FREE) SUFFIX 64-TERMINAL 0.5mm pitch PLASTIC PACKAGE 98ARL10571D ISSUE B
18730
Analog Integrated Circuit Device Data Freescale Semiconductor
33
PACKAGING PACKAGE DIMENSIONS
EP (Pb-FREE) SUFFIX 64-TERMINAL 0.5mm pitch PLASTIC PACKAGE 98ARL10571D ISSUE B 18730
34
Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS
EP (Pb-FREE) SUFFIX 64-TERMINAL 0.5mm pitch PLASTIC PACKAGE 98ARL10571D ISSUE B 18730
Analog Integrated Circuit Device Data Freescale Semiconductor
35
REVISION HISTORY
REVISION HISTORY
Revision 1.0 Date 10/2005 Description of Changes * Initial Release
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Analog Integrated Circuit Device Data Freescale Semiconductor
REVISION HISTORY
NOTES
18730
Analog Integrated Circuit Device Data Freescale Semiconductor
37
How to Reach Us:
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MPC18730 Rev 1.0 10/2005

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